As will be appreciated by those skilled in the art, as the design of electronic integrated circuit chips and devices has progressed, more and more circuitry is being disposed in increasingly dense patterns and it is becoming correspondingly more difficult to test such circuits. One methodology for performing chip test is described in U.S. Pat. No. 4,071,902 issued to Edward Eichelberger, et al. on Jan. 31, 1978 and assigned to the same assignee as the present invention and incorporated herein by reference. This patent describes the basic features of a level sensitive scan design (LSSD), which is used to facilitate circuit test. The circuits generally considered in LSSD include digital circuits having logic and memory functions used in the design and construction of digital signal processing and information handling systems and machines. Similarly, integrated circuit devices of interest typically possess blocks of combinatorial logic whose inputs and outputs are supplied to certain memory elements. In particular, in an LSSD system the memory elements or circuits comprise shift register latches (SRLs).
A prior art method referred to as self-test using MISR/Parallel SRSG (STUMPS) is used to test integrated circuit chips and devices. The acronym SRSG stands for the Shift Register Sequence Generator. Such devices are typically implemented as linear feedback shift registers. These registers generally comprise a chain of shift register elements in which Exclusive-OR elements in a feedback loop are provided so as to combine several intermediate latch output signals which are returned to the shift register input. The feedback paths are configured to result in the generation of a pseudo-random sequence of binary digits which are employed as test sequences for the above mentioned combinational circuits. The design and construction of pseudo-random pattern generators in the form of linear feedback shift registers is well known in the art. Output signals from the SRSG are fed through channels to a plurality of different scan paths. Each scan path comprises a plurality of shift register latches. The combinational logic output signals captured in the latch strings are supplied to a multiple input signature register or MISR. It will be appreciated by those skilled in the art, that the shift register latch elements also function in normal operation as, for example, sequential circuit memory elements in conjunction with combinatorial logic networks on, for example, a chip. During operation of the circuit in normal system environment, the shift register latches function as memory elements passing signals to be processed from one combinatorial block to another and at the same time typically receive input signals for subsequent application to combinatorial logic blocks in subsequent clock cycles. Thus the shift register latches play a significant role in establishing and defining stable logic outputs at appropriate points in a machine cycle. It is useful to keep in mind that the SRSG and the MISR are properly considered to be dedicated test elements. However, shift register latches serve a dual purpose which is more particularly apparent when considering the actual signal supplied to the shift register latches in normal operation.
This methodology has evolved mainly in support of LSSD logic and structural testing. The STUMPS structure shown in FIG. 1 illustrates a typical system and chip design that incorporates these concepts. See, for example, U.S. Pat. No. 5,150,366 assigned to the assignee of this patent.
Two basic components of this LBIST structure are a Linear Feedback Shift Register (LFSR) and a Multiple Input Signature Register (MISR). The LFSR serves as a pseudo random pattern generator that provides the stimuli for the logic being tested, while the MISR is utilized to generate a unique signature representing the responses from the logic. Ideally the signature for each failing device is different from the signature of a good device after a predefined number of test cycles.
The configuration of the scan chain in the LBIST test mode is partitioned into several sub-chains of approximately the same length. These chains are loaded and unloaded serially for each LBIST pattern. The pseudo random data loaded in parallel into each sub-chain is supplied by the LFSR and used as test stimuli. Similarly and simultaneously, the state of all latches in the sub-chains are unloaded serially into the MISR forming a signature representing the compressed data.
Each LBIST test pattern, in addition to the loading and unloading of the sub-chains, requires timed application of system clocks to launch the test vector from these latches through the combinational logic and capture the resulting response in the receiving latches. Since a typical system design may consist of several system clocks and various path delays, the clock test sequence and timing set-up may be applied multiple times with different clock combinations and timings. Typically, this is accomplished by an on-product clock generation (OPCG) function and LBIST control.
An LBIST test interval, in turn, consists of a relatively large number of these load/unload sequences followed each by the system clock cycles. At the end of the interval the MISR contents or signature is unloaded and compared to an expected signature. Several signature intervals may be applied to achieve the desired test coverage.
This LBIST methodology is an effective Design for Test (DFT) strategy that can support structural test from the chip level, various package levels, up to the system level. Some of the benefits associated with this approach include relatively low test data volumes, minimal VLSI test system requirements, at-speed test rates, and extendability to system test.
Alternatively, a disadvantage with this methodology is the lengthy test time required in loading and unloading a large number of pseudo random test patterns.